The present invention relates to method of making narrow lines of polycrystalline silicon which can be used, for example, as the gate of an MOS transistor and/or an interconnection conduction of an integrated circuit and semiconductor devices utilizing such narrow lines.
It is known to use polycrystalline silicon as the gate for MOS transistors and as an interconnection between MOS transistors and other electrical components of an integrated circuit. It is also known that it is desirable to have the gate of an MOS transistor as narrow as possible. Heretofore, the polycrystalline gates have generally been defined in width using standard photolithographic techniques which have a limit on the narrowness that can be achieved. Another technique which has been developed to define a polycrystalline gate is described in U.S. Pat. No. 3,738,880, to A. Laker, issued June 13, 1973, entitled "METHOD OF MAKING A SEMICONDUCTOR DEVICE." In this technique, a P-type dopant is diffused into a polycrystalline silicon layer through an opening in a masking layer, such as a silicon dioxide layer, to form a doped strip or line in the polycrystalline silicon layer. After removing the masking layer, the undoped portion of the polycrystalline silicon layer can be removed by an etchant which does not attack the doped strip, so as to leave the doped strip in the desired pattern. However, this technique is also limited as to the narrowness of the strip or line which can be formed both because of the techniques generally used to form the opening in the masking layer and because the dopant, when diffused into the polycrystalline silicon layer, spreads out laterally to form a doped line which is wider than the opening in the masking layer.